1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly to an array substrate for the LCD device having a thin film transistor of improved properties and a method of fabricating the array substrate.
2. Discussion of the Related Art
The LCD device uses optical anisotropy and polarization properties of liquid crystal molecules to display images. The liquid crystal molecules have directional orientation characteristics resulting from their thin and long shape. An arrangement direction of the liquid crystal molecules can be controlled by applying an electrical field to them. By controlling the arrangement direction of the liquid crystal molecules, light can be refracted along the arrangement direction of the liquid crystal molecules to display images.
In particularly, an LCD devices including a thin film transistor (TFT) as a switching element, and referred to as an active matrix LCD (AM-LCD) device, is well suited for implementing high resolution displays and for displaying moving images. A LCD device that includes the TFT as the switching element may be referred to a TFT-LCD device.
Generally, the TFT-LCD device includes an array substrate on which a TFT and a pixel electrode are formed, a color filter substrate on which a color filter layer and a common electrode are formed, and a liquid crystal layer. The array substrate and the color filter layer face and are spaced apart from each other, and a liquid crystal layer interposed therebetween is driven by an electric field induced between the pixel and common electrode.
FIG. 1 is a perspective plan view showing a pixel region of an array substrate for an LCD device according to the related art. In FIG. 1, a gate line 20, a gate electrode 36, an active layer 40, a source electrode 32 and a drain electrode 34, a data line 30, and a pixel electrode 50 are formed on a substrate 10 having a pixel region “P”. The gate and data lines 20 and 30 cross each other to define the pixel region “P”. The gate electrode 36 is connected to the gate line 20, and the active layer 40 is formed over the gate electrode 36. The source electrode 32 is connected to the data line 30 and spaced apart from the drain electrode 34. The gate electrode 36, the active layer 40, an ohmic contact layer (not shown), the source electrode 32 and the drain electrode 34 constitute a thin film transistor (TFT) “T”. Moreover, the pixel electrode 50 is formed in the pixel region “P” to be connected to the drain electrode 34 through a drain contact hole 38. An exposed portion of the active layer 40 between the source and drain electrodes 32 and 34 is defined as a channel region. Properties of the TFT “T” depend on the geometry of the channel region.
FIGS. 2A to 2D are cross-sectional views showing fabricating processes of a portion of the array substrate taken along the line II-II of FIG. 1. A switching region “S” is defined in the pixel region “P” and the TFT “T” is formed in the switching region “S”.
As shown in FIG. 2A, a first metal layer (not shown) is formed on a substrate 10 and patterned through a first mask process to form a gate line (not shown) and a gate electrode 36. The gate electrode 36 is disposed in the switching region “S”. A gate insulating layer 45 is formed on the substrate 10 including the gate line (not shown) and the gate electrode 36 by depositing an inorganic insulating material, such as silicon nitride (SiNe) and silicon oxide (SiO2).
Next, as shown in FIG. 2B, an intrinsic amorphous silicon layer (not shown) and an impurity-doped amorphous silicon layer (not shown) are sequentially formed on the gate insulating layer 45. The intrinsic amorphous silicon layer (not shown) and the impurity-doped amorphous silicon layer (not shown) are patterned through a second mask process to form an active layer 40 and an impurity-doped amorphous silicon pattern 41. The impurity-doped amorphous silicon pattern 41 is disposed on the active layer 40, and both the active layer 40 and the impurity-doped amorphous silicon pattern 41 have an island shape and overlap to the gate electrode 36. The active layer 40 and the impurity-doped amorphous silicon pattern 41 are located in the switching region “S”.
As shown in FIG. 2C, a second metal layer (not shown) is formed on the substrate 10 on which the active layer 40 and the impurity-doped amorphous silicon pattern 41 (of FIG. 2B) are formed by depositing a conductive metallic material such as copper (Cu), aluminum (Al), or Al alloy (AlNd). The second metal layer is patterned through a third mask process to form a data line (not shown), a source electrode 32 and a drain electrode 34. The data line crosses the gate line to define the pixel region “P”, and the source electrode 32 is connected to the data line. The source and drain electrodes 32 and 34 are spaced apart from each other and located in the switching region “S”. A portion of the impurity-doped amorphous silicon pattern 41 and the active layer 40 between the source and drain electrodes 32 and 34 may correspond to a center of the gate electrode 36. The impurity-doped amorphous silicon pattern 41 (of FIG. 2B) exposed between the source and drain electrodes 32 and 34 is removed using the source and drain electrodes 32 and 34 as a mask to form an ohmic contact layer 42 from the impurity-doped amorphous silicon pattern 41 (of FIG. 2B) exposing a portion of the active layer 40. The exposed portion of the active layer 40 is defined as a channel region “ch”.
As shown in FIG. 2D, a passivation layer 55 is formed on the source and drain electrodes 32 and 34 by depositing an inorganic insulating material, such as silicon nitride (SiNe) and silicon oxide (SiO2), and then patterned through a fourth mask process to form a drain contact hole 38 exposing a portion of the drain electrode 34. A transparent conductive material layer (not shown) is formed on the passivation layer 55 by depositing a transparent conductive material such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO), and then patterned through a fifth mask process to form a pixel electrode 50. The pixel electrode 50 is connected to the drain electrode 34 through the drain contact hole 38.
In the third mask process, the second metal layer (not shown) including one of Cu, Al and AlNd is wet-etched. During the wet-etching process, the second metal layer may be over-etched resulting in variation of the width; a critical dimension (CD) of the channel region “ch”. The width of the channel region, which is a distance between the source and drain electrodes, may vary from the desired value such that properties and of the TFT are degraded.
With reference to FIGS. 3A to 3D, the third mask process is explained in more detail. FIGS. 3A to 3D show details of the third mask process illustrated in FIG. 2C.
In FIG. 3A, the second metal layer 65 and a photosensitive material layer 70 are sequentially formed on the substrate 10 where the gate electrode 36, the gate insulating layer 45, the active layer 40 and the impurity-doped amorphous silicon pattern 41 are formed. The photosensitive material layer 70 may be a positive type in which an unexposed portion of the photosensitive material layer 70 is not developed (i.e., the unexposed portions are not removed developing). The mask “M” including a transmitting area “TA” and a blocking area “BA” is disposed over the photosensitive material layer 70. The transmitting area “TA” has a transmittance of about 100%, while the blocking area “BA” has a transmittance of about 0%. The blocking area “BA” corresponds to both end portions of the active layer 40, and the transmitting area “TA” is located between the blocking areas “BA”. In particular, the transmitting area “TA” corresponds to the gate electrode 36. Further, the blocking area “BA” corresponds to a portion where the second metal layer 65 is to remain. The photosensitive material layer 70 is exposed through the mask “M”, and thereby being developed.
As shown in FIG. 3B, the photosensitive material layer 70 (of FIG. 3A) corresponding to the transmitting area “TA” is removed to expose the second metal layer 65, while the photosensitive material layer 70 (of FIG. 3A) corresponding to the blocking area “BA” remains to form photosensitive material patterns 71 on the second metal layer 65.
Next, as shown in FIG. 3C, the second metal layer 65 (of FIG. 3B) is etched using the photosensitive material patterns 71 as an etching mask to form the source and drain electrodes 32 and 34 and to expose the impurity-doped amorphous silicon pattern 41. When the second metal layer 65 (of FIG. 3B) includes at least one of Cu, Al and AlNd, the second metal layer 65 (of FIG. 3B) is wet-etched. During wet-etching, the side portions B and C of the source and drain electrodes 32 and 34 are exposed to an etchant and become over-etched. Accordingly, a distance between the source and drain electrodes 32 and 34 is greater than a desired critical dimension “CD1”. That is, the distance between the source and drain electrodes 32 and 34 is greater than the distance between photosensitive material patterns 71.
Next, as shown in FIG. 3D, the exposed impurity-doped amorphous silicon pattern 41 (of FIG. 3C) is etched using the source and drain electrodes 32 and 34 to form the ohmic contact layer 42 from the impurity-doped amorphous silicon pattern 41 (of FIG. 3C) and expose the active layer 40. As mentioned above, the exposed active layer 40 is defined as the channel region “ch”. Since the distance between the source and drain electrodes 32 and 34 is greater than the desired critical dimension “CD1”, a width of the channel region “CD2” is also greater than the desired critical dimension “CD1”.
Typically, the desired critical dimension “CD1” is about 5 micrometers (μm), while the width of the channel region “CD2” is about 9 μm. The increased width of the channel region causes a deterioration of the properties of the TFT. Moreover, when fabricating an array substrate for the LCD device including an in-plane switching (IPS) mode, a decreased width of lines may cause problems such as a signal delay.